Compound semiconductor devices, such as Group III-V semiconductor devices, are ubiquitous in a wide variety of electronic components, particularly high-frequency components operating at radio frequency (RF), microwave and millimeter (mm) wave frequencies. One common type of compound semiconductor device is a gate-controlled device. Known gate-controlled devices include a metal semiconductor field effect transistor (MESFET), a high-electron mobility transistor (HEMT), and, to a lesser degree currently, a metal oxide semiconductor field effect transistor (MOSFET).
In an effort to improve the operational speed of these semiconductor devices as well as to increase the throughput per wafer during manufacture, there is a need to reduce the size of the devices. One way to reduce the size of the device is to reduce the size of the features of the device, such as the gate. Minimization of transistor gate dimensions is typically advantageous in a number of areas, particularly in minimizing gate capacitance, increasing maximum transistor current, and in increasing the maximum operating frequency of the transistor. In the silicon-based complementary metal oxide semiconductor (CMOS) processing, minimization of gate dimension (to at least 65 nm) is achieved using very expensive deep-UV (wavelengths of 193 nm and below) stepper-scanner tools, coupled with expensive phase shifting and optical proximity correction mask technologies.
While advantageous, methods used in reduced feature-size CMOS processing have not found acceptance in the compound semiconductor market, primarily because of unfavorable economics for high capital and mask costs at low production volumes. In addition, because of wafer flatness and topology issues in compound semiconductors, the methods used in Si processing may not be functional.
As a result, the most prevalent compound semiconductor industry solution for producing sub-0.25 μm compound semiconductor gates is e-beam lithography. E-beam lithographic tools have the disadvantage of being more costly than conventional optical patterning technologies. Moreover, because all features are fabricated in a time-consuming sequence rather than in large scale batch-mode processing, compound semiconductor devices fabricated by E-beam direct write methods enjoy a comparatively lower throughput. Furthermore, E-beam tools typically use a combined positive/negative resist stack in which a metal gate is evaporated and then lifted, producing a narrow but fragile vertical gate.
There is a need, therefore, for a method of fabricating compound semiconductor devices that overcomes at least the shortcoming of known methods discussed above.